DEFINITIONS AND DESIGN NOTES:
ADDITIONAL DESIGN NOTES:
1. Initial Input Offset Voltage is the offset voltage of the
ALD1722E/ALD1722 operational amplifier as shipped from the
factory. The device has been pre-programmed and tested for
programmability.
A. The ALD1722E/ALD1722 is internally compensated for unity
gainstabilityusinganovelschemewhichproducesasinglepole
role off in the gain characteristics while providing more than 70
degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD1722E/ALD1722 will typically drive 400pF
of external load capacitance; in the inverting unity gain configu-
ration, it can drive up to 800pF of load capacitance.
2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjust-
ment in either the positive or the negative direction of the input
offset voltage from an initial offset voltage. The input offset
programpins, VE1orVE2, changetheinputoffsetvoltageinthe
negativeorpositivedirection,respectively.Userspecifiedtarget
offset voltage can be any offset voltage within this programming
range.
B. The ALD1722E/ALD1722 has complementary p-channel
and n-channel input differential stages connected in parallel to
accomplish rail to rail input common mode voltage range. The
switching point between the two differential stages is 1.5V
above negative supply voltage. For applications such as invert-
ingamplifierornon-invertingamplifierwithagainlargerthan2.5
(5V operation), the common mode voltage does not make
excursions below this switching point. However, this switching
doestakeplaceiftheoperationalamplifierisconnectedasarail-
to-railunitygainbufferandthedesignmustallowforinputoffset
voltage variations.
3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming, when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.
4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usu-
ally this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
PSRR, CMRR, TCVos and noise. It can also include errors
introduced by external components, at a system level. Pro-
grammed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.
C. The output stage consists of class AB complementary output
drivers. The oscillation resistant feature, combined with the rail-
to-railinputandoutputfeature, makestheALD1722E/ALD1722
an effective analog signal buffer for high source impedance
sensors, transducers, and other circuit networks.
D. The ALD1722E/ALD1722 has static discharge protection.
However, care must be exercised when handling the device to
avoid strong static fields that may degrade a diode junction,
causing increased input leakage currents. The user is advised
to power up the circuit before, or simultaneously with, any input
voltages applied and to limit input voltages to not exceed 0.3V
of the power supply voltage levels.
5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.
E. VE1 and VE2 are high impedance terminals, as the internal
bias currents are set very low to a few microamperes to
conserve power. For some applications, these terminals may
need to be shielded from external coupling sources. For ex-
ample, digital signals running nearby may cause unwanted
offset voltage fluctuations. Care during the printed circuit board
layout to place ground traces around these pins and to isolate
them from digital lines would generally eliminate such coupling
effects. In addition, optional decoupling capacitors of 1000pF or
greater value can be added to VE1 and VE2 terminals.
6. Input Voltage Range is determined by two parallel comple-
mentary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one selected input bias
voltage. Dependingontheselectedinputbiasvoltagerelativeto
the power supply voltages, offset voltage trimming may affect
one or both input stages. For the ALD1722E/ALD1722, the
switching point between the two stages occur at approximately
1.5V above the negative supply voltage
F. The ALD1722E/ALD1722 is designed for use in low voltage,
micro-power circuits. The maximum operating voltage during
normaloperationshouldremainbelow10Voltsatalltimes.Care
should be taken to insure that the application in which the
devices are used would not experience any positive or negative
transient voltages that cause any of the terminal voltages to
exceed this limit.
7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.
8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
theoffsetvoltagefromPSRRandCMRRissettozerounderthe
specific power supply and common mode conditions, and
becomes part of the Programmed Input Offset Voltage Error.
G. All inputs or unused pins except VE1 and VE2 pins should be
connected to a supply voltage such as Ground so that they do
not become floating pins, since input impedance at these pins
is very high. If any of these pins are left undefined, they may
cause unwanted oscillation or intermittent excessive current
drain. As these devices are built with CMOS technology, normal
operating and storage temperature limits, ESD and latchup
handling precautions pertaining to CMOS device handling
should be observed.
9. Average Long Term Input Offset Voltage Stability is based on
input offset voltage shift through operating life test at 125
degrees C extrapolated to Ta = 25 degrees C, assuming
activation energy of 1.0eV. This parameter is sample tested.
10
Advanced Linear Devices
ALD1722E/ALD1722
ALD [ ADVANCED LINEAR DEVICES ]
