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ALD1722E_11 参数 Datasheet PDF下载

ALD1722E_11图片预览
型号: ALD1722E_11
PDF下载: 下载PDF文件 查看货源
内容描述: EPAD®低功耗CMOS运算放大器 [EPAD® LOW POWER CMOS OPERATIONAL AMPLIFIER]
分类和应用: 运算放大器
文件页数/大小: 13 页 / 107 K
品牌: ALD [ ADVANCED LINEAR DEVICES ]
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ADDITIONAL DESIGN NOTES:  
DEFINITIONS AND DESIGN NOTES:  
A. The ALD1722E is internally compensated for unity gain  
stability using a novel scheme which produces a single pole role  
off in the gain characteristics while providing more than 70  
degrees of phase margin at unity gain frequency. A unity gain  
buffer using the ALD1722E will typically drive 400pF of external  
load capacitance; in the inverting unity gain configuration, it can  
drive up to 800pF of load capacitance. At a gain of 5, the  
ALD1722E can drive up to 4000pF load capacitance, and is  
ideallysuitedforhighprecisionanalogsignaltransmittedacross  
a cable or a wiring harness applications.  
1. Initial Input Offset Voltage is the initial offset voltage of the  
ALD1722Eoperationalamplifierwhenshippedfrom thefactory.  
The device has been pre-programmed and tested for program-  
mability.  
2. Offset Voltage Program Range is the range of adjustment of  
user specified target offset voltage. This is typically an adjust-  
ment in either the positive or the negative direction of the input  
offset voltage from an initial input offset voltage. The input offset  
programming pins, VE1 or VE2, change the input offset voltage  
inthenegativeorpositivedirection, respectively. Userspecified  
target offset voltage can be any offset voltage within this pro-  
gramming range.  
B. The ALD1722E has complementary p-channel and n-chan-  
nel input differential stages connected in parallel to accomplish  
rail to rail input common mode voltage range. The switching  
point between the two differential stages is 1.5V above negative  
supply voltage. For applications such as inverting amplifiers or  
non-inverting amplifiers with a gain larger than 2.5 (5V opera-  
tion), the common mode voltage does not make excursions  
below this switching point.  
3. Programmed Input Offset Voltage Error is the final offset  
voltage error after programming when the Input Offset Voltage  
is at target Offset Voltage. This parameter is sample tested.  
4. Total Input Offset Voltage is the same as Programmed Input  
Offset Voltage, corrected for system offset voltage error. Usu-  
ally this is an all inclusive system offset voltage, which also  
includes offset voltage contributions from input offset voltage,  
C. The output stage consists of class AB complementary output  
drivers. The oscillation resistant feature, combined with the rail-  
to-rail input and output feature, makes the ALD1722E an effec-  
tive analog signal buffer for high source impedance sensors,  
transducers, and other circuit networks.  
PSRR, CMRR, TCV  
and noise. It can also include errors  
OS  
introduced by external components, at a system level. Pro-  
grammed Input Offset Voltage and Total Input Offset Voltage is  
not necessarily zero offset voltage, but an offset voltage set to  
compensate for other system errors as well. This parameter is  
sample tested.  
D. The ALD1722E has static discharge protection. However,  
caremustbeexercisedwhenhandlingthedevicetoavoidstrong  
static fields that may degrade a diode junction, causing in-  
creasedinputleakagecurrents. Theuserisadvisedtopowerup  
the circuit before, or simultaneously with, any input voltages  
applied and to limit input voltages not to exceed 0.3V of the  
power supply voltage levels.  
5. The Input Offset and Bias Currents are essentially input  
protection diode reverse bias leakage currents. This low input  
bias current assures that the analog signal from the source will  
not be distorted by it. For applications where source impedance  
is very high, it may be necessary to limit noise and hum pickup  
through proper shielding.  
E. VE1 and VE2 are high impedance terminals, as the internal  
biascurrentsaresetverylowtoafewmicroamperestoconserve  
power. For some applications, these terminals may need to be  
shielded from external noise coupling sources. For example,  
digital signals running nearby may cause unwanted offset volt-  
age fluctuations. Care during the printed circuit board layout, to  
place ground traces around these pins and to isolate them from  
digital lines, will generally eliminate such coupling effects. In  
addition, optional decoupling capacitors of 1000pF or greater  
value can be added to VE1 and VE2 terminals.  
6. Input Voltage Range is determined by two parallel comple-  
mentary input stages that are summed internally, each stage  
having a separate input offset voltage. While Total Input Offset  
Voltage can be trimmed to a desired target value, it is essential  
to note that this trimming occurs at only one user selected input  
bias voltage. Depending on the selected input bias voltage  
relative to the power supply voltages, offset voltage trimming  
may affect one or both input stages. For the ALD1722E, the  
switching point between the two stages occurs at approximately  
1.5V above negative supply voltage.  
F. The ALD1722E is designed for use in low voltage, low power  
circuits. The maximum operating voltage during normal opera-  
tion should remain below 10V at all times. Care should be taken  
toinsurethattheapplicationinwhichthedeviceisuseddoesnot  
experience any positive or negative transient voltages that  
cause any of the terminal voltages to exceed this limit.  
7. Input Offset Voltage Drift is the average change in Total Input  
Offset Voltage as a function of ambient temperature. This  
parameter is sample tested.  
8. Initial PSRR and initial CMRR specifications are provided as  
reference information. After programming, error contribution to  
the offset voltage from PSRR and CMRR is set to zero under the  
specific power supply and common mode conditions, and be-  
comes part of the Programmed Input Offset Voltage Error.  
G. All inputs or unused pins except VE1 and VE2 pins should be  
connected to a supply voltage such as Ground so that they do  
not become floating pins, since input impedance at these pins is  
veryhigh. Ifanyofthesepinsareleftundefined, theymaycause  
unwanted oscillation or intermittent excessive current drain. As  
thesedevicesarebuiltwithCMOStechnology,normaloperating  
and storage temperature limits, ESD and latchup handling  
precautions pertaining to CMOS device handling should be  
observed.  
9. Average Long Term Input Offset Voltage Stability is based on  
input offset voltage shift through operating life test at 125°C  
extrapolatedtoTA =25°C, assumingactivationenergyof1.0eV.  
This parameter is sample tested.  
ALD1722E  
Advanced Linear Devices  
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