ASAHI KASEI
[AK8817/18]
Input Control Register (R/W) [Address 0x04]
This is an out-of-standard quality input signal control register.
Sub Address 0x04
default Value 0x00
bit 7
Reserved
0
bit 6
CBCR
0
bit 5
VD2
0
bit 4
VD1
0
bit 3
VD0
0
bit 2
HD2
0
bit 1
HD1
0
bit 0
HD0
0
Adjustment of Sync input timing is made.
BIT Register Name
R/W
R/W
Definition
HDI signal input is delayed by the set value.
bit 0
~
bit 2
bit 3
~
HD0
~
HD2
VD0
HDI Input Delay
VDI Input Delay
HD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )
VDI signal input is delayed by the set value.
VD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )
~
R/W
bit 5
bit 6
bit 7
VD2
CBCR
Reserved
Exchange CbCr
Reserved
R/W Cb, Cr timing data are interchanged at CBCR = 1.
R/W Reserved
Rev.001E
43
2009 / 12
AKM [ ASAHI KASEI MICROSYSTEMS ]
