ASAHI KASEI
[AK5380]
SWITCHING CHARACTERISTICS (fs=4kHz~48kHz)
(Ta=-40~85°C; VA=4.5~5.5V; VD=2.7~5.5V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Control Clock Frequency
Master Clock 256fs:
fCLK
1.024
32
32
1.536
21
21
2.048
16
16
3.072
11
11
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
Pulse Width Low
Pulse Width High
768fs:
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fSLK
18.432
24.576
36.864
Pulse Width Low
Pulse Width High
SCLK Frequency
LRCK Frequency
6.144
48
MHz
kHz
fs
4
Serial Interface Timing
SCLK Period
(Note 12)
tSLK
160
65
65
30
30
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “• ”
SCLK “• ” to LRCK Edge
LRCK Edge to SDTO Valid (Note 14)
SCLK “¯” to SDTO Valid
tSLKL
tSLKH
tLRSH
tSHLR
tDLR
(Note 13)
(Note 13)
35
35
tDSS
Power-Down & Reset Timing
PDN Pulse Width
tPDW
tPDV
150
ns
1/fs
4129
PDN “• ” to SDTO delay
(Note 15)
Notes:
12. Refer to the operating overview section “Serial Data Interface”.
13. SCLK rising edge must not occur at the same time as LRCK edge.
14. In case of MSB justified format.
15. These cycles are the number of LRCK rising from PDN rising.
MS0100-E-01
2001/7
- 8 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
