[AK5357]
OPERATION OVERVIEW
■ System Clock
MCLK (256fs/384fs/512fs), SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be
synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency
and the system clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF), the input level (CMOS or TTL)
and master/slave are selected by CKS2-0 pins as shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not
provided, the AK5357 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5357 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless the PDN pin = “L”.
MCLK
fs
256fs
384fs
512fs
16.384MHz
22.5792MHz
24.576MHz
N/A
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
32kHz
44.1kHz
48kHz
8.192MHz
11.2896MHz
12.288MHz
24.576MHz
12.288MHz
16.9344MHz
18.432MHz
36.864MHz
96kHz
Table 1. System Clock Example (N/A: Not available)
CKS2
L
CKS1
L
CKS0
L
Input Level
CMOS
HPF Master/Slave
MCLK
SCLK
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
256fs (∼ 96kHz)
ON
Slave
Slave
≥ 48fs or 32fs
L
L
H
CMOS
OFF
≥ 48fs or 32fs
L
L
H
H
L
H
CMOS
CMOS
ON
ON
Master
Master
64fs
64fs
512fs (∼ 48kHz)
256/384fs (∼ 96kHz)
512/768fs (∼ 48kHz)
Reserved
H
L
L
TTL
ON
Slave
≥ 48fs or 32fs
H
H
H
L
H
H
H
L
H
CMOS
CMOS
ON
ON
Master
Master
64fs
64fs
384fs (∼ 96kHz)
768fs (∼ 48kHz)
Table 2. Mode Select
Note: SDTO outputs 16bit data at SCLK=32fs.
■ Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF pin
SDTO
24bit, MSB justified
24bit, I2S Compatible
LRCK
H/L
L/H
SCLK
Figure
Figure 1
Figure 2
L
H
≥ 48fs or 32fs
≥ 48fs or 32fs
Table 3. Audio Interface Format
MS0294-E-03
2009/03
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
