[AK5358B]
■ Power Down
The AK5358B is placed in power-down mode by bringing the PDN pin “L” or MCLK stop more than 13us, and the
digital filter is also reset at the same time. This reset should always be made after power-up. In power-down mode, the
VCOM is same level as VSS1. MCLK and LRCK must be input when the PDN pin is “H” to release the power down
mode. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes
available after 4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode.
During initialization, the ADC digital data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs
are settled in the data corresponding to the input signals after the end of initialization (Settling approximately takes the
same time as group delay).
(1)
PDN
Internal
State
Normal Operation
GD
Power-down
Initialize
Normal Operation
GD
(2)
A/D In
(Analog)
(3)
A/D Out
(Digital)
Idle Noise
Idle Noise
“0”data
“0”data
Clock In
MCLK,LRCK,SCLK
(4)
Figure 3. Power-down/up sequence example (PDN pin reset)
(1)
PDN
Internal
State
Normal Operation
GD
Power-down
Initialize
“0”data
Normal Operation
GD
(2)
A/DIn
(Analog)
(3)
“0”data
A/DOut
(Digital)
Idle Noise
Idle Noise
(5)
(6)
Clock In
MCLK
Figure 4. Power-down/up sequence example (MCLK stop reset)
Notes:
(1) 4132/fs in slave mode and 4129/fs in master mode.
(2) Digital output corresponding to analog input has the group delay (GD).
(3) A/D outputs “0” data at the power-down state.
(4) MCLK is input as normal operation.
(5) When MCLK is stopped more than 13us, the AK5358B becomes power down mode.
(6) MCLK and LRCK must be input to release power-down mode.
MS1155-E-00
2010/02
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
