[AK4753]
■ Limiter Operation
ALMT1 bit controls ON/OFF of the limiter operation of the DSP1 block. ALMT2 bit controls ON/OFF of the limiter
operation of the DSP2 block. DSP1 block and DSP2 block are controlled completely independent by Limiter Mode
Control, Timer Select and Reference Level control bits.
1. Limiter Movement
During a limiter operation, when either Lch or Rch exceeds the limiter detection level (Table 31), the VOL values
(same value for Lch and Rch) are attenuated automatically by the amount defined by the limiter ATT step set by
LMAT1-0 bits (Table 32).
When ZELMN bit = “0” (zero cross detection is enabled), LFSTN bit = “0” (fast limiter is enabled) and the output level
is less than full-scale, the VOL values (Lch and Rch) are changed by a limiter operation at the individual zero crossing
points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both limiter
and recovery operation (Table 33). When the output level exceeds full-scale, VOL values are immediately (Period: 1/fs)
changed. When LFSTN bit= “1” (fast limiter is disabled), VOL values are changed at the individual zero crossing point
of each channels or at the zero crossing timeout regardless of the output level.
When ZELMN bit = “1” (zero cross detection is disabled), VOL values are immediately (period: 1/fs) changed by a
limiter operation. Attenuation step is fixed to 1 step regardless of the LMAT1-0 bits setting.
After completing the attenuate operation, unless ALMT1 bit or ALMT2 bit is changed to “0”, the operation repeats
when the input signal level exceeds limiter detection level.
LMTH1 bit LMTH0 bit
Limier Detection Level
Limiter Output ≥ −2.5dBFS
Limiter Output ≥ −4.1dBFS
Limiter Output ≥ −6.0dBFS
Limiter Output ≥ −8.5dBFS
Recovery Waiting Counter Reset Level
−2.5dBFS > Limiter Output ≥ −4.1dBFS
−4.1dBFS > Limiter Output ≥ −6.0dBFS
−6.0dBFS > Limier Output ≥ −8.5dBFS
−8.5dBFS > Limier Output ≥ −12dBFS
0
0
1
1
0
1
0
1
(default)
Table 31. Limiter Detection Level / Recovery Counter Reset Level
Limiter ATT Step (0.375dB/step)
Limiter Output Limiter Output Limiter Output Limiter Output
LMAT1
bit
LMAT0
bit
≥ LMTH
≥ FS
≥ FS + 6dB
≥ FS + 12dB
0
0
1
1
0
1
0
1
1
2
2
1
1
2
4
2
1
2
4
4
1
2
8
8
(default)
Table 32. Limiter ATT Step
Zero Crossing Timeout Period
ZTM1 bit ZTM0 bit
8kHz
16ms
32ms
64ms
128ms
16kHz
8ms
16ms
32ms
64ms
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
0
0
1
1
0
1
0
1
128/fs
256/fs
512/fs
1024/fs
(default)
Table 33. Zero Crossing Timeout Period
MS1311-E-00
2011/07
- 44 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
