[AK4706]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP=11.4 ∼ 12.6V, VD1=VD2=4.75 ∼ 5.25V, VVD1=VVD2=VVD3=VVD4=4.75 ∼ 5.25V; CL = 20pF)
Parameter
Master Clock Frequency 256fs:
Duty Cycle
Symbol
fCLK
dCLK
fCLK
dCLK
fs
Min
8.192
40
12.288
40
typ
max
12.8
60
19.2
60
Units
MHz
%
MHz
%
kHz
%
384fs:
Duty Cycle
LRCK Frequency
Duty Cycle
32
45
50
55
Duty
Audio Interface Timing
BICK Period
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
312.5
100
100
50
50
50
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDTI Hold Time
(Note 19)
(Note 19)
50
SDTI Setup Time
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
tBUF
tHD:STA
-
1.3
0.6
400
-
-
kHz
μs
μs
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
-
-
-
-
0.3
0.3
-
μs
μs
μs
μs
μs
μs
μs
μs
ns
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 20)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
tF
tSU:STO
tSP
50
Reset Timing
PDN Pulse Width
(Note 21)
tPD
150
ns
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 21. The AK4706 should be reset by PDN pin = “L” upon power up.
Note 22. I2C-bus is a trademark of NXP B.V.
MS0507-E-01
2010/09
- 17 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
