ASAHI KASEI
[AK4704]
AKM CONFIDENTIAL
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP=11.4 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1=VVD2 = 4.75 ∼ 5.25V; CL = 20pF)
Parameter
Master Clock Frequency 256fs:
Duty Cycle
Symbol
fCLK
dCLK
fCLK
dCLK
fs
Min
2.048
40
3.072
40
typ
max
12.8
60
19.2
60
Units
MHz
%
MHz
%
kHz
%
384fs:
Duty Cycle
LRCK Frequency
Duty Cycle
8
45
50
55
Duty
Audio Interface Timing
BICK Period
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
312.5
100
100
50
50
50
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDTI Hold Time
(Note: 17)
(Note: 17)
50
SDTI Setup Time
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
tBUF
tHD:STA
-
1.3
0.6
400
-
-
kHz
µs
µs
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
-
-
-
-
0.3
0.3
-
µs
µs
µs
µs
µs
µs
µs
µs
ns
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note: 18)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
tF
tSU:STO
tSP
50
Reset Timing
PDN Pulse Width
(Note: 19)
tPD
150
ns
Note: 17. BICK rising edge must not occur at the same time as LRCK edge.
Note: 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 19. The AK4704 should be reset by PDN= “L” upon power up.
Note: 20. I2C is a registered trademark of Philips Semiconductors.
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent
to use the components in the I2C system, provided the system conform to the I2C specifications defined by
Philips.
Rev. 0.5
2004/1
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
