ASAHI KASEI
[AK4702EQ]
Note: 14. TVRC, TVG, TVB.
Note: 15. Refer the Figure 1.
R1
75 ohm
Video Signal Output
R2
75 ohm
C2
max: 15pF
C1
max: 400pF
Figure 1. Load Resistance R1+R2, and Load Capacitance C1 and C2.
Note: 16. AC load. Refer the Figure 2.
Video Signal Output
R1
20k ohm
(AC load)
C2
max: 15pF
Figure 2. Load Resistance R1 and Load Capacitance C1
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP=10.0 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1=VVD2 = 4.75 ∼ 5.25V; CL = 20pF)
Parameter
Master Clock Frequency 256fs:
Duty Cycle
Symbol
fCLK
dCLK
fCLK
dCLK
fs
Min
2.048
40
3.072
40
typ
max
12.8
60
19.2
60
Units
MHz
%
MHz
%
kHz
%
384fs:
Duty Cycle
LRCK Frequency
Duty Cycle
8
45
50
55
Duty
Audio Interface Timing
BICK Period
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
312.5
100
100
50
50
50
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDTI Hold Time
(Note: 17)
(Note: 17)
50
SDTI Setup Time
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
tBUF
tHD:STA
-
4.7
4.0
100
-
-
kHz
µs
µs
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
4.7
4.0
4.7
0
0.25
-
-
4.0
0
-
-
-
-
-
1.0
0.3
-
µs
µs
µs
µs
µs
µs
µs
µs
ns
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note: 18)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
tF
tSU:STO
tSP
50
Reset Timing
PDN Pulse Width
(Note: 19)
tPD
150
ns
MS0424-E-00
2005/09
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
