ASAHI KASEI
[AK4683]
No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin Name
LOUT2
ROUT2
LOUT1
ROUT1
VCOM
AVDD2
AVSS2
LISEL
LOPIN
ROPIN
RISEL
AVSS1
AVDD1
LIN1
RIN1
LIN2
RIN2
LIN3
RIN3
LIN4
RIN4
LIN5
RIN5
LIN6
RIN6
PVSS
R
I/O
O
O
O
O
-
-
-
O
O
O
O
-
-
I
I
I
I
I
I
I
I
I
I
I
I
-
-
Function
DAC2 Lch Positive Analog Output Pin
DAC2 Rch Positive Analog Output Pin
DAC1 Lch Positive Analog Output Pin
DAC1 Rch Positive Analog Output Pin
DAC/ADC Common Voltage Output Pin
2.2µF capacitor should be connected to AVSS2 externally.
DAC Power Supply Pin, 4.5V∼5.5V
DAC Ground Pin, 0V
Lch Feedback Resistor Output Pin
Lch Feedback Resistor Input Pin. 0.5 x AVDD1.
Rch Feedback Resistor Input Pin. 0.5 x AVDD1.
Rch Feedback Resistor Output Pin
ADC Ground Pin, 0V
ADC Power Supply Pin, 4.5V∼5.5V
Lch Input 1 Pin
Rch Input 1 Pin
Lch Input 2 Pin
Rch Input 2 Pin
Lch Input 3 Pin
Rch Input 3 Pin
Lch Input 4 Pin
Rch Input 4 Pin
Lch Input 5 Pin
Rch Input 5 Pin
Lch Input 6 Pin
Rch Input 6 Pin
PLL Ground pin
External Resistor Pin
12kΩ +/-1% resistor should be connected to PVSS externally.
Note: All input pins except internal biased pin (RX0) and analog input pins (LIN1-6, RIN1-6) should not be left
floating.
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Pin Name
RX0, LOUT1-2, ROUT1-2, LIN1-6, RIN1-6
INT, XTO, MCKO, VOUT/DZF/OVF, SDTOA-B,
CDTO, TX
RX1-3, CSN, CCLK, CDTI, XTI, MCLK2,
OLRCKA, ILRCKA, BICKA, SDTIA1-3,
LRCKB, BICKB, SDTIB
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
Digital
MS0427-E-01
-6-
2005/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
