[AK4685]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing (Slave Mode)
PORTA, C
BICKA,C Period
BICKA,C Pulse Width Low
Pulse Width High
LRCKA,C Edge to BICKA “↑” (Note 24)
BICKA,C “↑” to LRCKA Edge (Note 24)
SDTIA,C Hold Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
81
32
32
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
SDTIA,C Setup Time
PORTB
BICKB Period
BICKB Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
324
128
128
80
ns
ns
ns
ns
ns
ns
ns
LRCKB Edge to BICKB “↑” (Note 24)
BICKB “↑” to LRCKB Edge (Note 24)
LRCKB to SDTOB1,2 (MSB)
BICKB “↓” to SDTOB1,2
Audio Interface Timing (Master Mode)
BICKB Frequency
80
80
80
tBSD
fBCK
dBCK
tMBLR
tBSD
64fs
50
Hz
%
ns
ns
BICKB Duty
BICKB “↓” to LRCKB Edge
BICKB “↓” to SDTO
-40
40
20
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
tBUF
tHD:STA
-
1.3
0.6
400
-
-
kHz
μs
μs
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
0.6
0.6
0
0.1
-
-
0.6
-
-
-
-
-
-
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 25)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
0.3
0.3
-
50
400
tF
tSU:STO
tSP
Cb
0
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTOB1,2 valid
(Note 27)
(Note 28)
tPD
tPDV
150
ns
1/fs
522
Note 23. MCB supports only normal mode (256fsn, 384fsn, 512fsn, 768fsn).
Note 24. BICKA/B/C rising edge must not occur at the same time as LRCKA/B/C/ edge.
Note 25. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 26. I2C-bud is a trademark of NXP B.V.
Note 27. The AK4685 is reset by bringing the PND pin = “L”.
Note 28. This is the number of LRCKB rising from PDN rising.
MS1106-E-00
2009/08
- 14 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
