AK4671EG 参数 Datasheet PDF下载

[AK4671]

Serial Data Input A Pin

Serial Data Clock A Pin

Sync Signal A Pin

Serial Data Output A Pin

Digital I/O Power Supply 2 Pin, 1.6

∼

3.6V

Ground 2 Pin

PLLBT Power Supply Pin, 2.2

∼

3.6V

Output Pin for Loop Filter of PLLBT Circuit

E9 VCOCBT

O

This pin should be connected to VSS2 pin with one resistor and capacitor in series.

Output Pin for Loop Filter of PLL Circuit

D8 VCOC

O

This pin should be connected to VSS1 pin with one resistor and capacitor in series.

Common Voltage Output Pin, 0.5 x AVDD

D9 VCOM

O

Bias voltage of ADC inputs and DAC outputs.

Mute Time Constant Control Pin

C8 MUTET

O

Connected to VSS1 pin with a capacitor for mute time constant.

C9 ROUT2

O

Rch Headphone-Amp Output Pin

B9 LOUT2

O

Lch Headphone-Amp Output Pin

Test Pin

A9 TEST

-

This pin should be open.

A8 AVDD

-

Analog Power Supply Pin, 2.2

∼

3.6V

B8 VSS1

-

Ground 1 Pin

Rch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)

ROUT1

O

B7

Receiver-Amp Negative Output Pin (RCV bit = “1”: Receiver Output)

RCN

O

Lch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)

LOUT1

O

A7

Receiver-Amp Positive Output Pin (RCV bit = “1”: Receiver Output)

RCP

O

Rch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)

ROUT3

O

A6

Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)

LON

O

Lch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)

LOUT3

O

B6

Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)

LOP

O

RIN4

I

Rch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)

A5

I

Negative Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)

IN4−

LIN4

I

Lch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)

B5

IN4+

I

Positive Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)

RIN3

I

Rch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)

B4

I

Negative Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)

IN3−

LIN3

I

Lch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)

A4

IN3+

I

Positive Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)

RIN2

I

Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)

B3

I

Negative Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)

IN2−

LIN2

I

Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)

A3

IN2+

I

Positive Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)

RIN1

I

Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)

B2

I

Negative Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)

IN1−

LIN1

I

Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)

A2

IN1+

I

Positive Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)

No Connect Pin

C3 NC

-

No internal bonding. This pin should be open or connected to the ground.

Note 1. All input pins except analog input pins (MDT, LIN1/IN1+, RIN1/IN1−, LIN2/IN2+, RIN2/IN2−, LIN3/IN3+,

RIN3/IN3−, LIN4/IN4+, RIN4/IN4−, SAIN1, SAIN2, SAIN3) should not be left floating.

I/O pins except SDA pin (LRCK, BICK, SYNCA, BICKA, SYNCB, BICKB) should be processed appropriately.

Please refer the “Master

(P.45) and “PCM

(P.105). SDA pin

should be pulled-up by a resistor externally and be connected to (DVDD+0.3)V or less voltage.

No. Pin Name

J8 SDTIA

G8 BICKA

H9 SYNCA

G9 SDTOA

F8 TVDD2

F9 VSS2

E8 PVDD

I/O

I

I/O

I/O

O

-

-

-

Function

MS0666-E-02

-5-

2010/06