[AK4679]
3. Dynamic Range Control Block
The AK4679 has the dynamic range control (DRC) circuits. The compression level is selected in three levels and set by
DRCC1-0 bits (Table 65).
When the DRC is OFF (DRCC1-0 bits = “00”), the audio data passes this block by 0dB gain. However limiter and
recovery operation is always ON. The compression level must be set when PMDRC bit = “0”.
Low Mid
DRC Off
0dB
High
-6dB
-6dB
0dB
+3.5dB
DRC Input Level (dB)
Figure 75. DRC Gain Curve
DRCC1 bit
DRCC0 bit
Compression Level
0
0
1
1
0
1
0
1
OFF
Low
Middle
High
(default)
Table 65. DRC Compression Level Setting
1. DRC Limiter Operation
During the DRC limiter operation, when the output level of DRC exceeds full-scale, the DRC volume are attenuated
automatically with the soft transition in the attenuation speed set by DLMAT2-0 bits (Table 66).
DLMAT2 DLMAT1 DLMAT0
ATT Speed
16kHz
bit
bit
bit
8kHz
44.1kHz
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0.1dB/ms
0.3dB/ms
0.5dB/ms
1.1dB/ms
2.2dB/ms
4.5dB/ms
0.3dB/ms
0.5dB/ms
1.1dB/ms
2.2dB/ms
4.4dB/ms
9.0dB/ms
0.7dB/ms (default)
1.5dB/ms
3.0dB/ms
6.0dB/ms
12.2dB/ms
24.7dB/ms
1
1
1
1
0
1
N/A
Table 66. DRC ATT Speed Setting (N/A: Not available)
MS1402-E-06
2013/02
- 99 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
