[AK4679]
2. Interface
The input data channel of the DMDAT pin is set by DCLKP bit. When DCLKP bit = “1, Lch data is input to the
Decimation Filter if DMCLK = “H”, Rch data is input if DMCLK = “L”. When DCLKP bit = “0”, Rch data is input to the
Decimation Filter if DMCLK = “H”, Lch data is input if DMCLK = “L”. The DMCLK pin outputs “L” when DCLKE bit
= “0”, and only supports 64fs. In this case, necessary clocks must be supplied to the AK4679 for ADC operation. The
output data through “the Decimation and Digital Filters” is the negative full-scale with 0% 1’s density of 1bit output data
and positive full-scale with the 100% 1’s density of 1bit output data.
DCLKP bit
DMCLK pin = “H”
DMCLK pin = “L”
0
1
Rch
Lch
Lch
Rch
(default)
Table 25. Data In/Output Timing with Digital MIC
DMCLK(64fs)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 59. Data In/Output Timing with Digital MIC (DCLKP bit = “1”)
DMCLK(64fs)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 60. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)
MS1402-E-06
2013/02
- 65 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
