[AK4679]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=PVDD=1.7 ~ 2.0V, VDDE=1.1~1.3V, TVDDA=TVDDE=1.6 ~3 .6V, SVDD=3.0 ∼ 5.5V;
CL=20pF or 400pF (SDAA, SDAE pin); unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27
-
-
MHz
ns
ns
LRCK Output Timing
Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Output Timing
fs
-
-
-
Table 7
tBCK
50
-
-
-
kHz
ns
%
tLRCKH
Duty
Period
BCKO bit = “0”
BCKO bit = “1”
tBCK
tBCK
dBCK
-
-
-
1/(32fs)
1/(64fs)
50
-
-
-
ns
ns
%
Duty Cycle
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
8
tBCK−60
45
-
-
-
48
1/fs − tBCK
55
kHz
ns
%
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Input Timing
tLRCKH
Duty
Period
PLL3-0 bits = “0010”
PLL3-0 bits = “0011”
tBCK
tBCK
tBCKL
tBCKH
-
-
1/(32fs)
1/(64fs)
-
-
-
-
ns
ns
ns
ns
Pulse Width Low
Pulse Width High
0.4 x tBCK
0.4 x tBCK
-
-
MS1402-E-06
2013/02
- 23 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
