[AK4679]
■ Path & Mixing Setting of Digital Block (Figure 61)
PMADL, PMADR, PMDML and PMDMR bits set both ADC power management and output data selection. In case of
mono operation, the same data is output to both channel slots.
PMADL bit PMADR bit
ADC Lch data
All “0”
Rch Input Signal
Lch Input Signal
Lch Input Signal
ADC Rch data
All “0”
Rch Input Signal
Lch Input Signal
Rch Input Signal
0
0
1
1
0
1
0
1
(default)
Table 76. ADC Mono/Stereo Select (Analog MIC: DMIC bit = “0”)
PMDML bit PMDMR bit
ADC Lch data
All “0”
Rch Input Signal
Lch Input Signal
Lch Input Signal
ADC Rch data
All “0”
Rch Input Signal
Lch Input Signal
Rch Input Signal
0
0
1
1
0
1
0
1
(default)
Table 77. ADC Mono/Stereo Select (Digital MIC: DMIC bit = “1)
PFSEL bit select the input data of programmable filter.
PFSEL
Programmable Filter Input
0
1
ADC Output (selected by Table 76)
SDTI Input (selected by Table 84)
(default)
Table 78. Programmable Filter Input Signal Select
When ADM bit is “1”, ALC output data is output to both channels of SDTO and SVOLA as (L+R)/2, respectively.
ADM bit
Lch
L
(L+R)/2
Rch
R
(L+R)/2
0
1
(default)
Table 79. ALC Output Mono Mixing
PFSDO bit select the input data both SDTO and SVOLA.
PFSDO bit
SDTO and SVOLA Input
0
1
ADC Output (selected by Table 76)
Programmable Filter Output (selected by Table 79) (default)
Table 80. SDTO, SVOLA Input Signal Select
MS1402-E-06
2013/02
- 105 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
