[AK4646]
fs=8kHz
Operation
fs=44.1kHz
Operation
Register Name Comment
Data
01
0
Data
01
0
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
−4.1dBFS
Enable
32ms
−4.1dBFS
Enable
23.2ms
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
01
11
WTM2-0
*WTM2-0 bits should be the same data
as ZTM1-0 bits
001
32ms
100
46.4ms
OREF5-0
OVL7-0,
OVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC2
Maximum gain at recovery operation
28H
91H
+6dB
0dB
28H
91H
+6dB
0dB
Gain of VOL
Limiter ATT step
Fast Limiter Operation
Recovery GAIN step
Fast Recovery Speed
ALC enable
00
1
00
00
1
1 step
ON
1 step
4 times
Enable
00
1
00
00
1
1 step
ON
1 step
4 times
Enable
Table 33. Example of the ALC Setting (Playback)
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0, LFST
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Manual Mode
ALC bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
WR (IREF7-0)
(1) Addr=06H, Data=14H
(2) Addr=08H, Data=E1H
(3) Addr=09H&0CH, Data=E1H
* The value of IVOL should be
the same or smaller than REF’s
WR (IVL/R7-0)
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=28H
(5) Addr=07H, Data=21H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
ALC Operation
Note : WR : Write
Figure 29. Registers set-up sequence at ALC operation
MS0557-E-05
2011/01
- 42 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
