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AK4645AEZ 参数 Datasheet PDF下载

AK4645AEZ图片预览
型号: AK4645AEZ
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 解码器编解码器消费电路商用集成电路
文件页数/大小: 96 页 / 791 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK4645]  
min  
typ  
max  
-
Units  
Vpp  
Parameter  
Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20k)  
Maximum Input Voltage (Note 18)  
Gain (Note 19)  
-
1.98  
MIN Æ LOUT/ROUT  
LOVL bit = “0”  
0
+2  
20  
16.4  
+4.5  
dB  
dB  
dB  
dB  
4.5  
LOVL bit = “1”  
HPG bit = “0”  
HPG bit = “1”  
-
24.5  
-
-
15.5  
-
MIN Æ HPL/HPR  
Stereo Input: LIN2/RIN2/LIN4/RIN4 pins; LIN3/RIN3 pins (AIN3 bit = “1”)  
Maximum Input Voltage (Note 20)  
Gain  
-
1.98  
-
Vpp  
LIN/RIN Æ LOUT/ROUT  
LOVL bit = “0”  
LOVL bit = “1”  
HPG bit = “0”  
HPG bit = “1”  
0
+2  
0
+4.5  
dB  
dB  
dB  
dB  
4.5  
-
4.5  
-
-
+4.5  
-
LIN/RIN Æ HPL/HPR  
+3.6  
Full-differential Mono Input: IN4+/pins (L4DIF bit = “1”)  
Maximum Input Voltage (Note 21)  
Gain  
-
3.96  
-
Vpp  
LOVL bit = “0”  
LOVL bit = “1”  
LOVL bit = “0”  
LOVL bit = “1”  
HPG bit = “0”  
HPG bit = “1”  
dB  
dB  
dB  
dB  
dB  
dB  
IN4+/Æ LOUT/ROUT  
(LODIF bit = “0”)  
IN4+/Æ LOP/LON  
(LODIF bit = “1”, Note 22)  
IN4+/Æ HPL/HPR  
10.5  
6  
4  
0
+2  
6  
2.4  
1.5  
-
4.5  
-
10.5  
-
-
+4.5  
-
1.5  
-
Power Supplies:  
Power-Up (PDN pin = “H”)  
All Circuit Power-up:  
AVDD+DVDD+TVDD (Note 23)  
HVDD: HP-Amp Normal Operation  
No Output (Note 24)  
-
-
16  
5
24  
8
mA  
mA  
Power-Down (PDN pin = “L”) (Note 25)  
AVDD+DVDD+TVDD+HVDD  
-
1
100  
µA  
Note 18. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin  
/ 20k(typ).  
Note 19. The gain is in inverse proportion to external input resistance.  
Note 20. Maximum Input voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).  
Note 21. Maximum Input voltage is proportional to AVDD voltage. Vout = (IN4+) (IN4) = 1.2 x AVDD (typ). The  
signals with same amplitude and inverted phase should be input to IN4+ and IN4pins, respectively.  
Note 22. Vout = (LOP) (LON) at LODIF bit = “1”.  
Note 23. PLL Master Mode (MCKI=12.288MHz) and PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR =  
PMVCM = PMPLL = MCKO = PMMIN = PMMP = M/S bits = “1”. MPWR pin outputs 0mA.  
AVDD=11mA(typ), DVDD=3mA(typ), TVDD=2mA(typ).  
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=10mA(typ), DVDD=3mA(typ),  
TVDD=0.03mA(typ).  
Note 24. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN bits = “1”.  
Note 25. All digital input pins are fixed to TVDD or HVSS.  
MS0543-E-00  
2006/09  
- 10 -