ASAHI KASEI
[AK4645]
DC特性
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V)
Parameter
High-Level Input Voltage
Symbol
VIH
VIH
VIL
VIL
min
70%TVDD
75%TVDD
typ
max
-
-
Units
V
V
V
V
2.2V≤TVDD≤3.6V
1.6V≤TVDD<2.2V
2.2V≤TVDD≤3.6V
1.6V≤TVDD<2.2V
(Iout=−200µA)
-
-
-
-
-
Low-Level Input Voltage
-
-
30%TVDD
25%TVDD
-
High-Level Output Voltage
Low-Level Output Voltage
VOH
V
TVDD−0.2
VOL
VOL
Iin
-
-
-
-
-
-
0.2
0.4
±10
V
V
µA
(Except SDA pin: Iout=200µA)
(SDA pin: Iout=3mA)
Input Leakage Current
スイッチング特性
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; TVDD=1.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
tCLKL
tCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27
-
-
MHz
ns
ns
Pulse Width Low
Pulse Width High
MCKO Output Timing
Frequency
fMCK
0.2352
-
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
256fs at fs=32kHz, 29.4kHz
LRCK Output Timing
dMCK
dMCK
40
-
50
33
60
-
%
%
Frequency
fs
7.35
-
-
-
48
-
-
kHz
ns
%
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Output Timing
tLRCKH
Duty
tBCK
50
Period
BCKO bit = “0”
BCKO bit = “1”
tBCK
tBCK
dBCK
-
-
-
1/(32fs)
1/(64fs)
50
-
-
-
ns
ns
%
Duty Cycle
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
tCLKL
tCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27
-
-
MHz
ns
ns
Pulse Width Low
Pulse Width High
MCKO Output Timing
Frequency
fMCK
0.2352
-
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
256fs at fs=32kHz, 29.4kHz
LRCK Input Timing
dMCK
dMCK
40
-
50
33
60
-
%
%
Frequency
fs
7.35
tBCK−60
45
-
-
-
48
1/fs − tBCK
55
kHz
ns
%
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Input Timing
Period
tLRCKH
Duty
tBCK
tBCKL
tBCKH
1/(64fs)
0.4 x tBCK
0.4 x tBCK
-
-
-
1/(32fs)
ns
ns
ns
Pulse Width Low
Pulse Width High
-
-
MS0543-J-00
2006/09
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
