ASAHI KASEI
No. Pin Name
[AK4644]
PIN/FUNCTION
I/O
O
Function
1
MPWR
MIC Power Supply Pin
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
Analog Ground Pin
2
VCOM
O
3
4
AVSS
AVDD
-
-
Analog Power Supply Pin
Output Pin for Loop Filter of PLL Circuit (AIN3 bit = “0”: PLL is available)
This pin should be connected to AVSS with one resistor and capacitor in series.
Rch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available)
Control Mode Select Pin
VCOC
RIN3
I2C
O
I
5
6
7
I
“H”: I2C Bus, “L”: 3-wire Serial
Power-Down Mode Pin
PDN
I
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
Chip Select Pin (I2C pin = “L”: 3-wire Serial Mode)
Chip Address 1 Select Pin (I2C pin = “H”: I2C Bus Mode)
Control Data Clock Pin (I2C pin = “L”: 3-wire Serial Mode)
Control Data Clock Pin (I2C pin = “H”: I2C Bus Mode)
Control Data Input Pin (I2C pin = “L”: 3-wire Serial Mode)
CSN
I
I
I
I
I
8
CAD0
CCLK
SCL
CDTI
SDA
9
10
I/O Control Data Input Pin (I2C pin = “H”: I2C Bus Mode)
11 SDTI
12 SDTO
13 LRCK
14 BICK
15 DVDD
16 DVSS
17 MCKI
18 MCKO
I
O
Audio Serial Data Input Pin
Audio Serial Data Output Pin
I/O Input / Output Channel Clock Pin
I/O Audio Serial Data Clock Pin
-
-
I
O
Digital Power Supply Pin
Digital Ground Pin
External Master Clock Input Pin
Master Clock Output Pin
Test 1 Pin
This pin should be left floating.
Test 2 Pin
This pin should be left floating.
TEST1
TEST2
-
-
19
20
21 HVDD
22 HVSS
23 HPR
24 HPL
-
-
O
O
Headphone-Amp Power Supply Pin
Headphone-Amp Ground Pin
Rch Headphone-Amp Output Pin
Lch Headphone-Amp Output Pin
Mute Time Constant Control Pin
25 MUTET
O
Connected to HVSS pin with a capacitor for mute time constant.
Rch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output)
Receiver-Amp Negative Output Pin (RCV bit = “1”: BTL output)
Lch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output)
Receiver-Amp Positive Output Pin (RCV bit = “1”: BTL output)
Mono Signal Input Pin (AIN3 bit = “0”: PLL is available)
Lch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available)
ROUT
26
O
O
O
O
I
RCN
LOUT
RCP
27
MIN
LIN3
28
I
RIN2
IN2−
LIN2
IN2+
LIN1
IN1−
RIN1
IN1+
I
I
I
I
I
I
I
I
Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Microphone Negative Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
Microphone Positive Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
Microphone Negative Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
Microphone Positive Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
29
30
31
32
Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3) should not be left floating.
Note 2. AVDD or AVSS voltage should be input to I2C pin.
MS0477-E-01
2006/10
- 5 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
