ASAHI KASEI
[AK4644]
When writing to the IVL7-0 and IVR7-0 bits continuouslly, the control register should be written by an interval more than
zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write operation. If
the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and zero
crossing counter is not reset. Therefore, IVL and IVR can be written by an interval less than zero crossing timeout.
ALC bit
ALC Status
IVL7-0 bits
IVR7-0 bits
Internal IVL
Internal IVR
Disable
Enable
E1H(+30dB)
Disable
C6H(+20dB)
E1H(+30dB)
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
E1(+30dB) --> F1(+36dB)
E1(+30dB)
(1)
(2)
C6H(+20dB)
Figure 37. IVOL value during ALC operation
(1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. The wait time from
ALC bit = “1” to ALC operation start by IVL7-0 bits is at most recovery time (WTM2-0 bits) plus zerocross timeout
period (ZTM1-0 bits).
(2) Writing to IVL and IVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the IVOL
changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1”
by an interval more than zero crossing timeout period after ALC bit = “0”.
MS0477-E-01
2006/10
- 47 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
