ASAHI KASEI
[AK4644]
LRCK
0
1
2
3
9 10 11 12 13 14 15 0
1
2
3
9 10 11 12 13 14 15 0 1
BICK(32fs)
0 15 14
0 15 14
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0 15 14
0 15 14
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
SDTO(o)
SDTI(i)
0
1
2
3
15 16 17 18
31 0
1
2
3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
15 14
2
2
1
1
0
0
15 14
15 14
2
2
1
1
0
0
Don't Care
Don't Care
SDTI(i)
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 31. Mode 3 Timing
Mono/Stereo Mode
PMADL, PMADR and MIX bits set mono/stereo ADC operation. When MIX bit = “1”, EQ and FIL3 bits should be set to
“0”. ALC operation (ALC bit = “1”) or digital volume operation (ALC bit = “0”) is applied to the data in Table 19.
PMADL bit PMADR bit
MIX bit
ADC Lch data
All “0”
Rch Input Signal
Lch Input Signal
Lch Input Signal
(L+R)/2
ADC Rch data
All “0”
Rch Input Signal
Lch Input Signal
Rch Input Signal
(L+R)/2
0
0
1
0
1
0
x
x
x
0
1
Default
1
1
Table 19. Mono/Stereo ADC operation (x: Don’t care)
Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz
(@fs=44.1kHz) and scales with sampling rate (fs). When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is
enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is
enabled but the HPF of ADC is disabled.
MS0477-E-01
2006/10
- 35 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
