ASAHI KASEI
[AK4644]
PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the
AK4644 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 5).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 10) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (see Table 6)
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
AK4644
DSP or µP
MCKI
256fs/128fs/64fs/32fs
MCLK
BCLK
LRCK
MCKO
BICK
≥ 32fs
1fs
LRCK
SDTI
SDTO
SDTI
SDTO
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0477-E-01
2006/10
- 27 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
