ASAHI KASEI
[AK4641]
DC CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, BVDD=2.6 ∼ 3.6V)
Parameter
Symbol
min
typ
Max
Units
High-Level Input Voltage
Low-Level Input Voltage
Input Voltage at AC Coupling
High-Level Output Voltage
Low-Level Output Voltage
VIH
VIL
VAC
70%DVDD
-
50%DVDD
-
-
-
-
-
V
V
V
V
30%DVDD
(Note 18)
(Iout=−200µA)
-
-
VOH
DVDD−0.2
VOL
VOL
Iin
-
-
-
-
-
-
0.2
0.4
±10
V
V
µA
(Except SDA pin: Iout=200µA)
(SDA pin: Iout=3mA)
Input Leakage Current
Note 18. The external clock is input to MCLK pin via AC coupled capacitor.
SWITCHING CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, BVDD=2.6 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
16bit Stereo CODEC Interface Timing:
Master Clock Timing (MCLK pin)
Frequency
fCLK
tCLKL
tCLKH
tACW
1.792
-
-
-
-
12.288
MHz
ns
ns
Pulse Width Low
Pulse Width High
AC Pulse Width (Note 19)
0.4/fCLK
0.4/fCLK
0.4/fCLK
-
-
-
ns
LRCK Timing
Frequency
Duty Cycle
fs
Duty
7
45
-
-
48
55
kHz
%
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (Note 20)
BICK “↑” to LRCK Edge (Note 20)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
312.5
130
130
50
50
-
-
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDTI Hold Time
SDTI Setup Time
-
Note 19. Refer to Figure 3.
Note 20. BICK rising edge must not occur at the same time as LRCK edge.
MS0301-E-00
2004/05
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
