[AK4634]
■ Register Definitions
Addr Register Name
D7
PMPFIL
R/W
0
D6
PMVCM
R/W
D5
0
R
0
D4
PMSPK
R/W
0
D3
PMAO
R/W
0
D2
PMDAC
R/W
D1
0
R
0
D0
PMADC
R/W
00H
Power Management 1
R/W
Default
0
0
0
PMADC: ADC Block Power Control
0: Power down (default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle (1059/fs=133ms@8kHz) starts. After
initializing, digital data of the ADC is output.
PMDAC: DAC Block Power Control
0: Power down (default)
1: Power up
PMAO: Mono Line Out Power Control
0: Power down (default)
1: Power up
PMSPK: Speaker Block Power Control
0: Power down (default)
1: Power up
PMVCM: VCOM Block Power Control
0: Power down (default)
1: Power up
PMPFIL: Programmable Filter Block (HPF/ LPF/ 5-Band EQ/ ALC) Power Control
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” to each bit. When the PDN pin is “L”, all blocks are
powered-down.
When PMPLL and MCKO bits and all bits in 00H address are “0”, all blocks are powered-down.
When any of the blocks are powered-up, the PMVCM bit must be set to “1”. When PMPLL and MCKO bits and all
bits in 00H address are “0”, PMVCM bit can be “0”.
When any block of ADC, DAC, SPK, or Programmable digital filter is powered-up (PMADC bit = “1”or PMDAC bit
= “1” or PMSPK bit = “1” PMPFIL bit = “1”), the clocks must always be present.
Rev. 0.5
2007/10
- 62 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
