[AK4634]
OPERATION OVERVIEW
■ System Clock
There are the following five clock modes to interface with external devices. (Table 1 and Table 2)
Mode
PLL Master Mode
PMPLL bit M/S bit
PLL3-0 bit
Table 4
Figure
Figure 19
1
1
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: FCK or BICK pin)
EXT Slave Mode
1
0
Table 4
Table 4
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
1
0
0
0
0
1
x
x
EXT Master Mode
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
MCKO pin
MCKI pin
BICK pin
FCK pin
Master Clock
Input for PLL
(Note 29)
0
1
“L” Output
16fs/32fs/64fs
Output
1fs
Output
PLL Master Mode
256fs Output
Master Clock
Input for PLL
(Note 29)
0
1
“L” Output
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1fs
Input
≥ 16fs
Input
256fs Output
PLL Slave Mode 2
(PLL Reference Clock: FCK or BICK pin)
16fs/32fs/64fs
Input
1fs
Input
0
0
“L” Output
“L” Output
GND
256fs/
512fs/
1024fs
Input
1fs
Input
≥ 32fs
Input
EXT Slave Mode
256fs/
512fs/
1024fs
Input
32fs/64fs
Output
1fs
Output
EXT Master Mode
0
“L” Output
Note 29. 12MHz/13.5MHz/24MHz/27MHz
Table 2. Clock pins state in Clock Mode
Rev. 0.5
2007/10
- 23 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
