[AK4634]
Parameter
Symbol
min
typ
max
Units
EXT Master Mode (Figure 2)
MCKI Frequency: 256fs
512fs
fCLK
fCLK
fCLK
tCLKL
tCLKH
fFCK
fFCK
fFCK
dFCK
tBCK
tBCK
tBCK
dBCK
1.8816
2.048
12.288
MHz
MHz
MHz
ns
3.7632
4.096
13.312
1024fs
7.5264
8.192
13.312
Pulse Width Low
Pulse Width High
FCK Frequency (MCKI = 256fs)
(MCKI = 512fs)
0.4/fCLK
-
-
-
0.4/fCLK
-
ns
7.35
8
48
26
13
-
kHz
kHz
kHz
%
7.35
8
8
(MCKI = 1024fs)
Duty Cycle
7.35
-
-
-
-
-
50
BICK: Period (BCKO1-0 bit = “00”)
(BCKO1-0 bit = “01”)
(BCKO1-0 bit = “10”)
Duty Cycle
1/16fFCK
1/32fFCK
1/64fFCK
50
-
ns
-
ns
-
ns
-
%
Audio Interface Timing
DSP Mode: (Figure 3, Figure 4)
FCK “↑” to BICK “↑” (Note 22)
FCK “↑” to BICK “↓” (Note 23)
BICK “↑” to SDTO (BCKP bit = “0”)
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tDBF
tDBF
tBSD
tBSD
tSDH
tSDS
0.5 x tBCK−40
0.5 x tBCK−40
0.5 x tBCK
0.5 x tBCK + 40
ns
ns
ns
ns
ns
ns
0.5 x tBCK
0.5 x tBCK +40
−70
−70
50
-
-
-
-
70
70
-
SDTI Setup Time
50
-
Except DSP Mode: (Figure 5)
BICK “↓” to FCK Edge
FCK to SDTO (MSB)
tBFCK
tFSD
−40
−70
-
-
40
70
ns
ns
(Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
tBSD
tSDH
tSDS
−70
50
-
-
-
70
-
ns
ns
ns
SDTI Setup Time
50
-
Note 21. Duty Cycle = (the width of “L”)/(the period of clock)*100
Note 22. MSBS, BCKP bits = “00” or “11”
Note 23. MSBS, BCKP bits = “01” or “10”
Note 24. BICK rising edge must not occur at the same time as FCK edge.
Rev. 0.5
2007/10
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
