[AK4634]
3. PLL Slave Mode (MCKI pin)
Example
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
(1)
PMPLL bit
(Addr:01H, D0)
MCKO :
Sampling Frequency:48kHz
Enable
(1)
MCKO bit
(Addr:01H, D1)
(1) Addr:01H, Data:00H
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 69. Clock Stopping Sequence (3)
<Example>
(1) Power down of the PLL: PMPLL bit = “1” → “0”
Stop the MCKO output: MCKO bit = “1” → “0”
(2) Stop an external master clock
4. EXT Slave Mode
Example
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
(1)
Input Master Clock Select at PLL Mode: 12MHz
External MCKI
Input
MCKO :
Enable
Sampling Frequency:48kHz
(1)
(1)
External BICK
External FCK
Input
Input
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 70. Clock Stopping Sequence (4)
<Example>
(1) Stop an external master clock
■ Power Down
VCOM should be powered-down after the master clock is stopped if clocks are supplied when all blocks except for
VCOM are powered-down. The AK4634 is also powered-down by the PDN pin = “L”. In this case, the registers are
initialized.
MS0983-E-00
2008/07
- 85 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
