[AK4634]
■ Stop of Clock
Master clock can be stopped when ADC, DAC and Programmable Filter are not in operation.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO : Enable
Sampling Frequency:48kHz
(1)
PMPLL bit
(Addr:01H, D0)
(1) (2) Addr:01H, Data:08H
(2)
MCKO bit
(Addr:01H, D1)
"H" or "L"
Stop an external MCKI
(3)
External MCKI
Input
Figure 67. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock
2. PLL Slave Mode (FCK, BICK pin)
Example
Audio I/F Format: DSP Mode BCKP = MSBS = “0”
PLL Reference clock: BICK
(1)
PMPLL bit
(Addr:01H,D0)
BICK frequency: 64fs
Sampling Frequency: 48kHz
(2)
External BICK
External FCK
Input
Input
(1) Addr:01H, Data:00H
(2)
(2) Stop the external clocks
Figure 68. Clock Stopping Sequence (2)
<Example>
(1) Power down of the PLL: PMPLL bit = “1” → “0”
(2) Stop an external master clock
MS0983-E-00
2008/07
- 84 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
