[AK4634]
3. When the external clock (MCKI pin) is used in PLL Slave mode.
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO :
Enable
Sampling Frequency:48kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(3)
(2)
(2)Addr:04H, Data:68H
Addr:05H, Data:23H
PMVCM bit
(Addr:00H, D6)
(4)
PMPLL bit
(Addr:01H, D0)
(5)
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:03H
MCKO output start
MCKI pin
Input
20msec(max)
(6)
MCKO pin
(7)
Output
Input
(8)
BICK pin
FCK pin
BICK and FCK input start
Figure 61. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4634.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits must be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4) PLL Power Up: PMPLL bit “0” → “1”
(5) PLL lock time is 20ms(max) after the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin)
is supplied.
(6) Normal clock is output from the MCKO pin after PLL is locked.
(7) The invalid frequency is output from the MCKO pin during this period.
(8) BICK and FCK clocks should be synchronized with MCKO clock.
MS0983-E-00
2008/07
- 78 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
