[AK4634]
2. When the external clock (FCK or BICK pin) is used in PLL Slave mode.
Example:
Audio I/F Format: DSP Mode BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 48kHz
Power Supply
(1)
4fs of
(1) Power Supply & PDN pin = “L” Æ “H”
PDN pin
(3)
(2)
PMVCM bit
(2) Addr:04H, Data:38H
Addr:05H, Data:20H
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D0)
(3) Addr:00H, Data:40H
(4) Addr:01H, Data:01H
BICK and FCK input
FCK pin
BICK pin
Input
(4)
Internal Clock
(5)
Figure 60. Clock Set Up Sequence (2)
<Example>
(1)After Power Up: PDN pin “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4634.
(2)DIF1-0, FS3-0, PLL3-0, MSBS and BCKP bits must be set during this period.
(3)Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4)PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clocks (FCK or BICK pin) are
supplied. PLL lock time is 160ms(max) when PLL reference clock is FCK, and PLL lock time is 2ms(max) when
PLL reference clock is BICK.
(5)Normal operation starts after the PLL is locked.
MS0983-E-00
2008/07
- 77 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
