[AK4634]
CONTROL SEQUENCE
■ Clock Set up
When ADC, DAC, SPK-amp and Programmable Filter are used, the clocks must be supplied.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
MCKO : Enable
Power Supply
PDN pin
(1)
Sampling Frequency:48kHz
(2)
(3)
PMVCM bit
(Addr:00H, D6)
(1) Power Supply & PDN pin = “L” Æ “H”
(4)
MCKO bit
(Addr:01H, D1)
(2)Addr:01H, Data:01H
Addr:04H, Data:6AH
Addr:05H, Data:23H
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
Input
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:0BH
M/S bit
(Addr:01H, D3)
20msec(max)
(6)
(9)
BICK pin
FCK pin
Output
Output
(7)
1msec (max)
MCKO, BICK and FCK output
20msec(max)
(8)
MCKO pin
Figure 59. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4634.
(1)DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits must be set during this period.
(2) Power Up VCOM: PMVCM bit = “0” → “1”
VCOM should first be powered-up before the other block operates.
(2) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(3)PLL lock time is 20ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(4)The AK4634 starts to output the FCK and BICK clocks after the PLL becomes stable and the normal operation
starts.
(5)The invalid frequencies are output from FCK and BICK pins during this period.
(6)The invalid frequency is output from the MCKO pin during this period.
(7)The normal clock is output from the MCKO pin after the PLL is locked.
MS0983-E-00
2008/07
- 76 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
