[AK4634]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block. When ADCPF bit = “1”, ALC operation is enable at
recording path. When ADCPF bit = “0”, ALC operation is enable at playback path. ON/OFF switching of ALC operation
is controlled by ALC1 bit for recording and ALC2 bit for playback.
1. ALC Limiter Operation
During the ALC limiter operation, if the output data exceeds the ALC limiter detection level (Table 25), the volume value
is automatically attenuated by the amount defined in LMAT1-0 bits (Table 26).
When ZELMN bit = “0” (zero cross detection valid), the IVL and VOL value is changed by ALC limiter operation at the
individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout
period of both ALC limiter and recovery operation (Table 27). When ALC output level exceeds full-scale at LFST bit =
“1”, VOL value is immediately (Period: 1/fs) changed in 1 step. When ALC output level is less than full-scale, VOL value
is changed at the individual zero crossing point of each channels or at the zero crossing timeout.
When ZELMN bit = “1” (zero cross detection invalid), IVL and IVR values are immediately (period: 1/fs) changed by
ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input signal
level exceeds the ALC limiter detection level.
LMTH1 LMTH0 ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level
0
0
1
1
0
1
0
1
ALC Output ≥ −2.5dBFS
ALC Output ≥ −4.1dBFS
ALC Output ≥ −6.0dBFS
ALC Output ≥ −8.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
(default)
Table 25. ALC Limiter Detection Level / Recovery Waiting Counter Reset Level
ALC1 Limiter ATT Step
LMAT1
LMAT0
ALC1 Output ALC1 Output ALC1 Output ALC1 Output
≥ LMTH
≥ FS
≥ FS + 6dB
≥ FS + 12dB
0
0
1
1
0
1
0
1
1
2
2
1
1
2
4
2
1
2
4
4
1
2
8
8
(default)
Table 26. ALC Limiter ATT Step Setting
Zero Crossing Timeout Period
ZTM1
ZTM0
8kHz
16ms
32ms
64ms
128ms
16kHz
8ms
16ms
32ms
64ms
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
0
0
1
1
0
1
0
1
128/fs
256/fs
512/fs
1024/fs
(default)
Table 27. ALC Zero Crossing Timeout Period Setting
MS0983-E-00
2008/07
- 43 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
