[AK4627]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4627, are MCLK, LRCK and BICK. MCLK should be
synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS0 and DFS1 bits (Table 1). The frequency of MCLK at
each sampling speed is set automatically. (Table 2, Table 3, Table 4). In Auto Setting Mode (ACKS bit= “1”), as MCLK
frequency is detected automatically (Table 5) and the internal master clock becomes the appropriate frequency (Table 6),
it is not necessary to set DFS bits.
The AK4627 is automatically placed in power saving mode when MCLK or LRCK is stopped during normal operation
mode, and the analog output goes to VCOM (typ). When MCLK and LRCK are input again, the AK4627 is powered up.
After exiting reset following power-up, the AK4627 is not fully operational until MCLK and LRCK are input.
DFS1
DFS0
Sampling Speed (fs)
0
0
1
0
1
0
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
(default)
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK (MHz)
384fs
BICK (MHz)
64fs
256fs
8.1920
11.2896
12.2880
512fs
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
2.0480
2.8224
3.0720
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
MCLK (MHz)
192fs
BICK (MHz)
64fs
128fs
256fs
88.2kHz
96.0kHz
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
5.6448
6.1440
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At Double speed mode(DFS1 bit= “0”, DFS0 bit= “1”), 128fs and 192fs are not available for ADC.)
LRCK
fs
MCLK (MHz)
BICK (MHz)
64fs
128fs
192fs
256fs
176.4kHz
192.0kHz
22.5792
24.5760
-
-
-
-
11.2896
12.2880
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
(Note: At Quad speed mode(DFS1bit= “1”, DFS0 bit= “0”) are not available for ADC.)
MS1278-E-02
2012/03
- 15 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
