[AK4629]
Parameter
Symbol
min
typ
max
Unit
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
tBUF
-
400
-
-
-
-
-
-
-
1.0
0.3
-
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
(Note 19)
tF
tSU:STO
tSP
Cb
0.6
0
-
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
pF
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO1-2 valid
(Note 20)
(Note 21)
tPD
tPDV
150
ns
1/fs
522
Note 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 20. The AK4629 can be reset by bringing the PDN pin “L” to “H” upon power-up.
Note 21. These cycles are the number of LRCK rising from the PDN pin rising edge.
Note 22. I2C-bus is a trademark of NXP B.V.
MS1277-E-02
2012/03
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
