[AK4614]
■ Audio Serial Interface Format
When TDM1-0 bits = “00”, ten modes can be selected by the DIF2-0 bits as shown in Table 11. In all modes the serial data
is MSB-first, 2’s compliment format. The data SDTO1-3 is clocked out on the falling edge of BICK and the SDTI1-6 is
latched on the rising edge of BICK.
Mode3/4/8/9/13/14/18/19/23/24/28/29/33/34/38/39 in SDTI input formats can be used for 16-20bit data by zeroing the
unused LSBs.
LRCK
I/O
BICK
Mode M/S TDM1 TDM0 DIF2 DIF1 DIF0 SDTO1-3
24bit, Left
SDTI1-6
I/O
I
16bit, Right
justified
20bit, Right
justified
24bit, Right
justified
0
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
H/L
H/L
H/L
I
I
I
≥ 32fs
justified
24bit, Left
justified
24bit, Left
justified
I
I
≥ 48fs
≥ 48fs
24bit, Left
justified
24bit, Left
justified
3
4
5
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
H/L
L/H
H/L
I
I
I
I
≥ 48fs
≥ 48fs
64fs
24bit, I2S
24bit, Left
justified
24bit, I2S
16bit, Right
justified
(default)
O
O
24bit, Left
justified
24bit, Left
justified
20bit, Right
justified
24bit, Right
justified
6
7
1
1
0
0
0
0
0
0
0
1
1
0
H/L
H/L
O
O
64fs
64fs
O
O
24bit, Left
justified
24bit, Left
justified
8
9
1
1
0
0
0
0
0
1
1
0
1
0
H/L
L/H
O
O
64fs
64fs
O
O
24bit, I2S
24bit, I2S
Table 11. Audio data formats (Stereo mode)
Note. TVDD1 which is the Power of I/O buffer should be kept in the range of 1.6V~3.6V at Normal Speed Mode in Stereo
Mode. TVDD1 should be kept in the range of 3.0V~3.6V at Double Speed Mode and Quad Speed Mode.
MS1025-E-00
2008/10
- 32 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
