欢迎访问ic37.com |
会员登录 免费注册
发布采购

AK4614VQ 参数 Datasheet PDF下载

AK4614VQ图片预览
型号: AK4614VQ
PDF下载: 下载PDF文件 查看货源
内容描述: 6月12日声道音频编解码器 [6/12-Channel Audio CODEC]
分类和应用: 解码器编解码器消费电路商用集成电路
文件页数/大小: 69 页 / 1257 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
 浏览型号AK4614VQ的Datasheet PDF文件第23页浏览型号AK4614VQ的Datasheet PDF文件第24页浏览型号AK4614VQ的Datasheet PDF文件第25页浏览型号AK4614VQ的Datasheet PDF文件第26页浏览型号AK4614VQ的Datasheet PDF文件第28页浏览型号AK4614VQ的Datasheet PDF文件第29页浏览型号AK4614VQ的Datasheet PDF文件第30页浏览型号AK4614VQ的Datasheet PDF文件第31页  
[AK4614]  
OPERATION OVERVIEW  
System Clock  
It is possible to select the clock source either extra clock input or X’tal input for the AK4614. (Figure 17, Figure 18) The  
external clocks which are required to operate the AK4614 in slave mode are MCLK, LRCK and BICK. MCLK should be  
synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting  
Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each  
sampling speed is set automatically. (Table 3, Table 4, Table 5). In Auto Setting Mode (ACKS bit= “1”), as MCLK  
frequency is detected automatically (Table 6) and the internal master clock attains the appropriate frequency (Table 7), so  
it is not necessary to set DFS.  
In master mode, only MCLK is required. Master Clock Input Frequency should be set with the CKS1-0 bits, and the  
sampling speed should be set by the DFS1-0 bits. The frequencies and the duties of the clocks (LRCK, BICK) are not  
stabile immediately after setting CKS1-0 bits and DFS1-0 bits up.  
After exiting reset at power-up in slave mode, the AK4614 is in power-down mode until MCLK and LRCK are input.  
If the clock is stopped, click noise occurs when restarting the clock. Mute the digital output externally if the click noise  
influences system applications.  
DFS1  
DFS0  
Sampling Speed Mode (fs)  
(default)  
0
0
1
1
0
1
0
1
Normal Speed Mode  
32kHz~48kHz  
64kHz~96kHz  
128kHz~192kHz  
-
Double Speed Mode  
Quad Speed Mode  
N/A  
(N/A: Not available)  
Table 1. Sampling Speed (Manual Setting Mode)  
CKS1  
CKS0  
Normal Speed  
Mode  
Double Speed  
Mode  
Quad Speed  
Mode  
128fs  
128fs  
128fs  
128fs  
0
0
1
1
0
1
0
1
256fs  
384fs  
512fs  
512fs  
256fs  
256fs  
256fs  
256fs  
(default)  
Table 2. Master Clock Input Frequency Select (Master Mode)  
LRCK  
fs  
32.0kHz  
44.1kHz  
48.0kHz  
MCLK (MHz)  
384fs  
BICK (MHz)  
256fs  
8.1920  
11.2896  
12.2880  
512fs  
64fs  
12.2880  
16.9344  
18.4320  
16.3840  
22.5792  
24.5760  
2.0480  
2.8224  
3.0720  
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)  
MS1025-E-00  
2008/10  
- 27 -  
 
 复制成功!