[AK4616]
スイッチング特性
(Ta=-40∼+85°C; A3V31, A3V32= D3V3=3.0∼ 3.6V; D1V8=1.7∼ 1.9V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
Master Clock Timing
External Clock
256fs:
fCLK
2.048
32
32
3.072
22
22
4.096
16
16
12.288
18.432
24.576
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
Pulse Width Low
Pulse Width High
LRCK Timing (Slave mode)
Stereo mode
tCLKL
tCLKH
(TDM bit = “0”)
LRCK frequency
Duty Cycle
fs
Duty
8
45
48
55
kHz
%
TDM256 mode
(TDM bit = “1”)
LRCK frequency
“H” time
“L” time
fs
tLRH
tLRL
8
48
kHz
ns
ns
1/256fs
1/256fs
Audio Interface Timing (Slave mode)
Stereo mode (TDM bit = “0”)
BICK Period
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
324
130
130
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 12)
(Note 12)
BICK “↑” to LRCK Edge
20
LRCK to SDTO(MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
80
80
50
50
SDTI Setup Time
TDM256 mode
(TDM bit = “1”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
SDTO Setup time BICK “↑”
SDTO Hold time BICK “↑”
SDTI Hold Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSS
tBSH
tSDH
tSDS
81
33
33
23
23
6
5
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 12)
(Note 12)
SDTI Setup Time
Note 12. この規格値はLRCKのエッジとBICKの“↑” が重ならないように規定しています。
MS1437-J-01
2012/11
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
