ASAHI KASEI
[AK4584]
SWITCHING CHARACTERISTICS
(Ta=−10 70°C; AVDD, DVDD, PVDD=4.75 5.25V, TVDD=2.7 5.25V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Crystal Resonator
External Clock
Frequency
11.2896
11.2896
24.576
36.864
MHz
MHz
ns
Frequency
fCLK
tCLKL
tCLKH
Pulse Width Low
Pulse Width High
0.4/fCLK
0.4/fCLK
ns
MCKO1 Output
MCKO2 Output
Frequency
fMCK
dMCK
11.2896
40
24.576
60
MHz
%
Duty Cycle (Note 15)
50
50
Frequency
Duty Cycle
fMCK
dMCK
5.6448
40
18.432
60
MHz
%
PLL Clock Recover Frequency
fPLL
32
192
kHz
LRCK Frequency
Normal Speed Mode (DFS0=“0”, DFS1=“0”)
Double Speed Mode (DFS0=“1”, DFS1=“0”)
Quad Speed Mode (DFS0=“0”, DFS1=“1”)
fsn
fsd
fsq
32
88.2
176.4
45
48
96
kHz
kHz
kHz
%
192
55
Duty Cycle
Slave mode
Master mode
50
%
Audio Interface Timing
Slave mode
BICK Period
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
81
33
33
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
(Note 16)
(Note 16)
20
20
tBSD
tSDH
tSDS
20
20
SDTI Setup Time
Master mode
BICK Frequency
fBCK
dBCK
tMBLR
tBSD
64fs
50
Hz
%
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
SDTI Hold Time
−20
−20
20
20
20
ns
ns
ns
ns
tSDH
SDTI Setup Time
tSDS
20
Note: 15. Duty cycle is not guaranteed when using the external clock input.
Note: 16. BICK rising edge must not occur at the same time as LRCK edge.
MS0118-E-00
2001/11
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
