ASAHI KASEI
[AK
4584]
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
MCKO1
MCKO2
SDTO
SDTI
BICK
LRCK
M/S
DZF
VCOM
LOUT
ROUT
AVSS
AVDD
VREF
RIN
LIN
PVDD
R
PVSS
RX1
TEST1
RX2
O
O
O
I
I/O
I/O
I
O
O
O
O
-
-
I
I
I
-
-
-
I
I
I
Master Clock Output 1 Pin
Master Clock Output 2 Pin
Audio Serial Data Output Pin
Audio Serial Data Input Pin
Audio Serial Data Clock Pin
Input / Output Channel Clock Pin
Master / Slave Mode Pin
“H” : Master Mode, “L” : Slave Mode
Zero Input Detect Pin
Common Voltage Output Pin, AVDD/2
Bias voltage of ADC inputs and DAC outputs.
Lch Analog Output Pin
Rch Analog Output Pin
Analog Ground Pin
Analog Power Supply Pin, 4.75
∼
5.25V
Voltage Reference Input Pin, AVDD
Used as a voltage reference by ADC & DAC. VREF is connected externally to
filtered AVDD.
Rch Analog Input Pin
Lch Analog Input Pin
PLL Power Supply Pin, 4.75
∼
5.25V
External Resistor Pin for PLL
13kΩ
±
1% resistor should be connected to PVSS externally.
PLL Ground Pin
Receiver Input 1 with Amp for 0.2Vpp
Test 1 Pin
(Internal pull-down pin)
Receiver Input 2 with Amp for 0.2Vpp
Note: All input pins except pull-down pins should not be left floating.
MS0118-J-01
-6-
2001/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
