ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, HVDD = 2.5 ~ 3.6V: CL = 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
tCLKL
tCLKH
tACW
2.048
24.576
MHz
ns
ns
Pulse Width Low
Pulse Width High
AC Pulse Width
LRCK Timing
Frequency
(Note 20)
(Note 20)
(Note 21)
0.4/fCLK
0.4/fCLK
0.4/fCLK
ns
fs
Duty
8
45
44.1
48
55
kHz
%
Duty Cycle
Serial Interface Timing (Note 22)
BICK Period
BICK Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
325.5
130
130
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
LRCK Edge to BICK “• ”
BICK “• ” to LRCK Edge
LRCK to SDTO(MSB)
BICK “¯” to SDTO
SDTI Hold Time
(Note 23)
(Note 23)
50
80
80
50
50
SDTI Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CSN “H” Time
CSN “• ” to CCLK “• ”
CCLK “• ” to CSN “• ”
Power-down & Reset Timing
PDN Pulse Width
tCSH
(Note 24)
(Note 25)
tPD
tPDV
150
ns
1/fs
2081
PMADC “• ” to SDTO valid
Note 20. Except AC coupling.
Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 4.)
Note 22. Refer to “Serial Data Interface”.
Note 23. BICK rising edge must not occur at the same time as LRCK edge.
Note 24. The AK4566 can be reset by bringing PDN= “L” to “H” only upon power up.
Note 25. This is the count of LRCK “• ” from PMADC bit=”1”.
REV 0.5
2002/2
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
