ASAHI KASEI
AKM CONFIDENTIAL
[AK4561]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=VD=2.6 ~ 3.3V; VT=1.8 ~ 3.3V; CL=20pF)
Parameter Symbol
Control Clock Frequency
min
typ
max
Units
Master Clock(MCLK) 256fs: Frequency
Pulse Width Low
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
2.048
28
28
3.072
23
23
12.288
12.8
MHz
ns
ns
MHz
ns
ns
Pulse Width High
384fs: Frequency
Pulse Width Low
Pulse Width High
18.432
19.2
Channel Select Clock (LRCK): Frequency
Duty
8
45
48
50
50
55
kHz
%
Duty
Audio Interface Timing
BCLK Period
tBLK
tBLKL
tBLKH
tLRB
tBLR
tLRM
tBSD
312.5
130
130
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
BCLK Pulse Width Low
Pulse Width High
LRCK Edge to BCLK “• ” (Note 30)
BCLK “• ” to LRCK Edge (Note 30)
LRCK to SDTO(MSB) Delay Time
BCLK “¯” to SDTO Delay Time
SDTI Latch Hold Time
SDTI Latch Set up Time
Control Interface Timing
CCLK Period
50
80
80
tSDH
tSDS
50
50
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Latch Set Up Time
CDTI Latch Hold Time
CS “H” Time
CS ”¯” to CCLK “• ”
CCLK “• ” to CS “• ”
Reset Timing
tCSH
PD Pulse Width
PD “• ” to SDTO Delay Time (Note 31)
tPDW
tPDV
150
ns
1/fs
8224
Note 30. BCLK rising edge must not occur at the same time as LRCK edge.
Note 31. These cycles are the numbers of LRCK rising from PDN pin rising.
Rev. 0.9
2000/09
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
