ASAHI KASEI
[AK4555]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=1.6
∼
3.6V; C
L
=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
256fs/384fs/512fs/768fs
fCLK
2.048
1024fs
fCLK
2.048
Duty Cycle
dCLK
40
LRCK Timing
Frequency
fs
8
Duty Cycle
Duty
45
Serial Interface Timing
tSCK
1/(96fs)
SCLK Period
(8kHz
≤
fs
≤
33kHz)
tSCK
312.5
(33kHz < fs
≤
50kHz)
SCLK Pulse Width Low
tSCKL
130
Pulse Width High
tSCKH
130
(Note 8)
tLRS
50
LRCK Edge to SCLK “↑”
(Note 8)
tSLR
50
SCLK “↑” to LRCK Edge
tDSS
-
SCLK “↓” to SDTO
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Reset Timing
PWADN or PWDAN Pulse Width
tPW
150
(Note 9)
tPWV
-
PWADN “↑” to SDTO Valid
Note 8. SCLK rising edge must not occur at the same time as LRCK edge.
Note 9. These cycles are the number of LRCK rising from PWADN rising.
typ
-
-
-
44.1
-
-
-
-
-
-
-
-
-
-
-
2081
max
38.4
25.6
60
50
55
-
-
-
-
-
-
80
-
-
-
-
Units
MHz
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
MS0363-E-01
-7-
2005/08
AKM [ ASAHI KASEI MICROSYSTEMS ]
