[ASAHI KASEI]
[AK4544A]
General Description
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AC ‘97 Connection to the Digital AC ’97 controller
2AC ‘97 communicates with its companion AC ‘97 controller via a digital serial link, AC-link”. All digital audio streams, and
command/status information are communicated over this point to point serial interconnect. A breakout of the signals connecting the
two is shown in the following figure.
AC’97
Controller
AC’97
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
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Digital Interface
The AK4544A incorporates a 5 pin digital serial interface that links it to the AC ’97 controller. AC-link is a bi-directional, fixed
rate(48kHz), serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses
employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12
incoming data streams, each with 20-bit sample resolution. DAC and ADC resolution of the AK4544A is 18 bit resolution. The data
streams currently defined by the AC ‘97 specification include:
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PCM Playback
2 channel composite PCM output stream
PCM Record data
2 channel composite PCM input stream
Control
Control register write port
Status
Control register read port
6 output slots(One codec can use 2 slots out of 6 slots)
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2 input slots
2 output slot
2 input slots
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SYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the
necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each
rising edge of BIT_CLK. The receiver of AC-link data, the AK4544A for outgoing data and AC ’97 controller for incoming data,
samples each serial bit on the falling edges of BIT_CLK.
The AK4544A outputs BIT_CLK when it is assigned as Primary codec by codec ID configuration ID1# pin and ID0# pin. The other
hand, the AK4544A receives BIT_CLK when assigned as the Secondary codec.
The AC-link protocol provides for a special 16-bit slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot
within the current audio frame. A“1” in a given bit position of slot 0 indicates that the corresponding time slot within the current audio
frame has been assigned to a data stream, and contains valid data. If a slot is “Tagged” invalid, it is the responsibility of the source
of the data, (The AK4544A for the input stream, AC ’97 controller for the output stream), to stuff all bit positions with 0’s during that
slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where
SYNC is high is defined as the “Tag Phase”. The remainder of the audio frame where SYNC is low is defined as the “Data Phase”.
Note that SDATA_OUT and SDATA_IN data is delayed one BIT_CLK because AC’97 controller causes SYNC
signal high at a rising edge of BIT_CLK which initiates a frame.
“Output” stream means the direction from AC’97 controller to the AK4544A, and “Input” stream means the direction
from the AK4544A to AC’97 controller
2All the following sentences written with small italic font in this document quote the AC’ 97 component specification.
<MS0026-E-00>
2000/04
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
