ASAHI KASEI
[AK4536]
Parameter
Power Supplies
Power Up (PDN = “H”)
All Circuit Power-up: (Note 16)
AVDD+DVDD
SVDD: Speaker-Amp Normal Operation
(SPPS bit = “1”, No Output)
Power Down (PDN = “L”) (Note 17)
AVDD+DVDD+SVDD
min
typ
max
Units
10
9
10
15
18
200
mA
mA
µA
Note 4. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ)
Note 5. When IPGA Gain is changed, this typical value changes between 8kΩ and 11kΩ.
Note 6. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)
Note 7. When a PLL reference clock is FCK pin in PLL Slave Mode, S/(N+D) is 60dB (typ).
Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)
Note 9. Input signal of MIN pin is 1.98Vpp.
Note 10. There are no relations with the setup of SPKG bit, and it is the same value.
Note 11. The maximum input voltage of the BEEP input shows output from AOUT.
Note 12. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.66 x AVDD (max)
Note 13. When ALC2 Gain is changed, this typical value changes between 22kΩ and 26kΩ.
Note 14. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)
Note 15. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and
capacitive load.
Note 16. PLL Master Mode (X’tal = 12.288MHz) and PMMIC = PMADC = PMDAC = PMSPK = PMVCM = PMPLL =
PMXTL = PMAO = PMBP = M/S = “1”. And output current from MPI pin is 0mA. When the AK4536 is EXT
mode (PMPLL = PMXTL = M/S = “0”), “AVDD+DVDD” is typically 8mA.
Note 17. All digital input pins are fixed to DVDD or DVSS.
MS0174-E-00
-7-
2002/09
AKM [ ASAHI KASEI MICROSYSTEMS ]
