ASAHI KASEI
[AK4534]
DC CHARACTERISTICS
(Ta=- 10 ~ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ~ 3.6V)
Parameter
Symbol
VIH
VIL
VAC
VOH
min
70%DVDD
-
50%DVDD
DVDD- 0.2
typ
Max
-
30%DVDD
Units
V
V
V
V
High-Level Input Voltage
Low-Level Input Voltage
Input Voltage at AC Coupling
High-Level Output Voltage
Low-Level Output Voltage
-
-
-
-
(Note 22)
(Iout=- 200mA)
-
-
VOL
VOL
-
-
0.2
0.4
V
V
-
-
(Except SDA pin: Iout=200mA)
(
SDA pin: Iout= 3mA)
Input Leakage Current
Iin
-
-
±10
mA
Note 22. When AC coupled capacitor is connected to MCKI pin.
SWITCHING CHARACTERISTICS
(Ta=- 10 ~ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ~ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Crystal Resonator Frequency
11.2896
2.048
0.4/fCLK
0.4/fCLK
0.4/fCLK
-
-
12.288
12.288
MHz
MHz
ns
ns
ns
External Clock
Frequency
fCLK
tCLKL
tCLKH
tACW
Pulse Width Low
Pulse Width High
AC Pulse Width (Note23)
MCKO Output
Frequency
Duty Cycle : except fs=32kHz
fs=32kHz at 256fs (Note 24)
fMCK
dMCK
dMCK
0.256
40
12.288
60
MHz
%
%
50
33
LRCK Frequency
Frequency
fs
Duty
Duty
8
45
48
55
kHz
%
%
Duty Cycle
Slave mode
Master mode
50
Audio Interface Timing
Slave mode
BICK Period
BICK Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
312.5
130
130
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
LRCK Edge to BICK “• ”
BICK “• ” to LRCK Edge
(Note 25)
(Note 25)
50
LRCK to SDTO (MSB) (Except I2S mode)
BICK “¯” to SDTO
SDTI Hold Time
80
80
50
50
SDTI Setup Time
Master mode
BICK Frequency
BICK Duty
BICK “¯” to LRCK
BICK “¯” to SDTO
SDTI Hold Time
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
64fs
50
Hz
%
ns
ns
ns
ns
- 80
- 80
50
80
80
SDTI Setup Time
50
Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 2)
Note 24. PMPLL bit = “1”.
Note 25. BICK rising edge must not occur at the same time as LRCK edge.
MS0133-E-03
2003/5
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
