ASAHI KASEI
[AK4522]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=4.5
∼
5.5V, VD=2.7
∼
5.5V; C
L
=20pF)
Parameter
Symbol
min
Master Clock Timing
4.096
fCLK
External Clock
256fs:
27
tCLKL
Pulse Width Low
27
tCLKH
Pulse Width High
6.144
fCLK
384fs:
20
tCLKL
Pulse Width Low
20
tCLKH
Pulse Width High
8.192
fCLK
512fs:
15
tCLKL
Pulse Width Low
15
tCLKH
Pulse Width High
LRCK
Frequency
fsn
16
Duty Cycle
dfs
45
Serial Interface Timing
Slave mode
160
tSCK
SCLK Period
65
tSCKL
SCLK Pulse Width Low
65
tSCKH
Pulse Width High
45
tLRS
LRCK Edge to SCLK “↑”
(Note 13)
45
tSLR
SCLK “↑” to LRCK Edge
(Note 13)
tLRM
LRCK to SDTO(MSB)
tSSD
SCLK “↓” to SDTO
40
tSDH
SDTI Hold Time
25
tSDS
SDTI Setup Time
Reset Timing
PD Pulse Width
tPD
150
PD “↑” to SDTO valid
(Note 14)
tPDV
Note 13. SCLK rising edge must not occur at the same time as LRCK edge.
14. These cycles are the number of LRCK rising from PD rising.
The AK4522 can be reset by bringing PD “L”.
typ
max
12.288
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
%
18.432
24.576
44.1
48
55
40
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
516
M0020-E-02
-7-
2012/01
AKM [ ASAHI KASEI MICROSYSTEMS ]
