ASAHI KASEI
[AK4528]
Parameter
Control Interface Timing (P/S=“L”)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “L” Time
CSN “↑” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
RSTADN “↑” to SDTO valid
PDN “↑” to SDTO valid
(Note 13)
(Note 14)
(Note 15)
Symbol
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSW
tCSS
tCSH
tPD
tPDV
tPDV
min
200
80
80
40
40
150
150
150
50
150
typ
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
1/fs
516
516
Note: 13. The AK4528 can be reset by bringing PDN “L”.
14. In serial mode, these cycles are the number of LRCK rising from RSTADN bit.
15. In parallel mode, these cycles are the number of LRCK rising from PDN pin.
Timing Diagram
1/fCLK
VIH
VIL
tCLKH
1/fs
VIH
VIL
MCLK
tCLKL
LRCK
tBCK
VIH
VIL
tBCKH
tBCKL
BICK
Clock Timing
MS0011-E-01
-9-
2004/01
AKM [ ASAHI KASEI MICROSYSTEMS ]
