ASAHI KASEI
[AK4527B]
Digital Ground
Analog Ground
1
2
3
4
5
6
7
8
9
SDOS
I2C
DZF2/OVF 33
32
31
RIN+
RIN-
System
Controller
SMUTE
BICK
LIN+ 30
LIN-
29
LRCK
SDTI1
SDTI2
SDTI3
SDTO
AK4527B
28
27
ROUT1
LOUT1
ROUT2 26
25
24
23
LOUT2
ROUT3
LOUT3
10 DAUX
11 DFS
Figure 11. Ground Layout
Note: AVSS and DVSS must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
The AK4527B requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up
sequence is not critical. AVSS and DVSS of the AK4527B must be connected to analog ground plane. System analog
ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit
board. Decoupling capacitors should be as near to the AK4527B as possible, with the small value ceramic capacitor being
the nearest.
2. Voltage Reference Inputs
The voltage of VREFH sets the analog input/output range. VREFH pin is normally connected to AVDD with a 0.1µF
ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic
capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from
VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM pins in order to avoid
unwanted coupling into the AK4527B.
3. Analog Inputs
The ADC inputs are differential. Figures 12 and 13 are circuit examples which analog signal is input by single end
(ADIF= “L”). The signal can be input from either positive or negative input and the input signal range scales with the
supply voltage and nominally 0.6 x VREFH Vpp. In case of single ended input, the distortion around full scale degrades
compared with differential input (ADIF= “H”). Figures 14 and 15 are circuit examples which analog signal is input to
both positive and negative input and the input signal range scales with the supply voltage and nominally 0.3 x VREFH
Vpp. The AK4527B can accept input voltages from AVSS to AVDD. The ADC output data format is 2’s complement.
The output code is 7FFFFFH(@24bit) for input above a positive full scale and 800000H(@24bit) for input below a
negative fill scale. The ideal code is 000000H(@24bit) with no input signal. The DC offset is removed by the internal
HPF.
The AK4527B samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples
of 64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not
have significant energy at 64fs.
MS0056-E-00
2000/10
- 28 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
